View TA1296FN_1321210.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TA1296FN
Preliminary
TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic
TA1296FN
Down-Converter IC with PLL for Satellite Tuner
The TA1296FN is a wideband down-converter which can operate at input frequency ranging from 850 MHz to 2200 MHz. Intended primarily for use in satellite tuners, this IC includes an oscillator, a mixer, an IF amplifier and a PLL. The I2C bus data format is used as the data control format. The supply voltage of 5.0 V helps minimize the tuner's power dissipation, while the compact 30-pin SSOP package allows the tuner to be kept small.
Features
* * * * * * * * * * * * * * * Supply voltage: 5.0 V (typ.) Wide input frequency range Low phase noise oscillator Standard I2C bus format control 4-MHz (X'tal) buffer output pin Reference oscillator input change-over switch [X'tal or external input] 33-V high-voltage tuning amplifier built-in 3-bit input port (for read mode) 2-bit band switch drive transistor (for write mode) 5-level AD converter Frequency step: 62.5 kHz or 125 kHz (for 4-MHz X'tal) 4-address setting via address selector Power-on reset circuit x1/2 prescaler Flat compact package: SSOP30-P-300-0.65 (0.65-mm pitch) Weight: 0.17 g (typ.)
Power-On Reset Operation Conditions
* * * * * Frequency step: 125 kHz Charge pump output current: 50 mA Counter data: all [0] Band driver: OFF Tuning amplifier: OFF Note 1: This device can easily be damaged by high voltages or electrical fields. For this reason, please handle it with care.
1
2002-02-12
TA1296FN
Block Diagram
SDA in/out Band2 out Band1 out
ADR set
XO SW
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ADR XO-SW Band Driver
Programmable Counter 1/2 1/32 1/33
Data Interface
Phase Comparator
Divider
ADC Charge Pump 1 GND1 2 VCC1 3 OSC-E 4 OSC-B 5 GND2 6 Vt-out 7 NF 8 X'tal 9 VCC2 10 XO buff out 11 GND3 12 ADC in 13 I-P1 in
Comparator
14 I-P2 in
15 I-P3 in
2
2002-02-12
SCL in
RF in2
RF in1
GND7
GND6
GND5
IF out
VCC4
VCC3
VCC3
TA1296FN
Pin Functions
Pin No. 1 2 Pin Name GND1 VCC1 Function Ground pin for oscillator circuit block Power supply pin for local oscillator circuit block 2 Interface 3/4
3 Oscillator 4 Local oscillator circuit
4 3
GND1 5 GND2 Ground pin for oscillator circuit block VCC2 6 Vt Output 6 Tuning voltage output pin with built-in tuning amplifier GND3 7 NF 7 VCC2 VCC2 1 kW 5 kW 5 kW 5 kW 5 kW 50 W 3/4
Crystal oscillator input Reference Input 8 (4-MHz input) Can be switched between X'tal oscillator and external input using pin 24 (XO switch).
8
1 kW
GND3 9 VCC2 Power supply pin for PLL circuit block VCC2 3/4
10
Reference signal buffer output
Buffer output pin for reference signal
10
GND3 11 GND3 Ground pin for PLL circuit block 3/4
3
2002-02-12
TA1296FN
Pin No. Pin Name Function VCC2 2 kW AD converter pin 12 ADC Converts input voltage into digital data. 12 Interface
GND3 13 I-P1 VCC2
13, 15 15 I-P3
GND3 Comparator status can be checked in Read Mode. VCC2
14
I-P2
14
GND3
VCC2
16
SCL Input
Input pin for I C bus serial clock data
2
16
1 kW 100 W
GND3
VCC2
SDA 17 Input/Output
Input/output pin for I C bus serial clock data
2
17
20 W
1 kW 100 W
GND3
70 kW
4
2002-02-12
TA1296FN
Pin No. Pin Name Function VCC2 18 Band 1 Output 18, 19 Output can be controlled by setting band switch data. 19 Band 2 Output GND3 20 GND4 Ground pin for IF amplifier circuit block 3/4 VCC3 Interface
21
IF Output
IF output pin
21
GND4 22 23 VCC3 GND5 Power supply pin for IF amplifier circuit block Ground pin for IF amplifier circuit block VCC2 25 kW 25 kW GND3 VCC2 150 kW 100 W 3/4 25 100 W 1 kW 50 kW GND3 26 GND6 Ground pin for mixer circuit block Determines reference signal input. 24 XO Switch If connected to ground: X'tal oscillator. If open or connected to VCC2: external input 24 1 kW 3/4 3/4
25
ADR Set
The address for hardware bit setting can be selected by applying voltage to this pin. 4 programmable address can be programmed.
5
2002-02-12
TA1296FN
Pin No. Pin Name Function Interface
27
RF Input1 RF signal input pin Input can be either balanced or unbalanced.
27 3 kW 3 kW
28
28
RF Input2 GND7
29 30
GND7 VCC4
Ground pin for mixer circuit block Power supply pin for mixer circuit block
3/4 3/4
6
2002-02-12
TA1296FN
Absolute Maximum Ratings (Ta = 25C)
Parameter Pin No. 2 Supply voltage 9 22 30 Tuning amplifier voltage Power dissipation Operating temperature Storage temperature 6 3/4 3/4 3/4 Symbol VCC1 VCC2 VCC3 VCC4 VBT PD Topr Tstg Rating 6 6 6 6 38 1130 mW (Note 2) -20 to 85 -55 to 150 C C V V Unit
Note 2: 50 mm 50 mm 1.6 mm, 40% Cu board If Ta > 25C, derate this value by 9.1 mW/C.
Recommended Operating Conditions
Pin No. 2 9 22 30 Symbol Local oscillator block PLL block IF amplifier block Mixer block VCC1 VCC2 VCC3 VCC4 Min 4.5 4.5 4.5 4.5 Typ. 5.0 5.0 5.0 5.0 Max 5.5 5.5 5.5 5.5 Unit V V V V
Electrical Characteristics
DC Characteristics (unless otherwise specified, VCC1 = VCC2 = VCC3 = VCC4 = 5 V, Ta = 25C) When power on, counter data = all [0], VBT = OFF, CP1 = CP0 = 0 and band = all [0]
Parameter Symbol ICC1 Power supply current ICC2 ICC3 ICC4 Total ICC-total 3/4 1 Test Circuit Test Condition 3/4 3/4 3/4 3/4 3/4 Min 5.0 16.0 16.5 9.5 47.0 Typ. 7.5 20.0 20.0 12.5 60.0 Max 10.0 25.5 24.5 16.0 76.0 mA mA Unit
7
2002-02-12
TA1296FN
Down-Converter Block
AC Characteristics (unless otherwise specified, VCC1 = VCC2 = VCC3 = VCC4 = 5 V, Ta = 25C)
Parameter RF input frequency RF input level IF output frequency IF output impedance Local oscillator frequency Conversion gain CG (Note 3) 2 (Note 3) Symbol Mfin MPin Afin AZout LO Test Circuit 3/4 3/4 3/4 3/4 3/4 Single-end 3/4 fRF = 898 MHz fRF = 1598 MHz fRF = 2198 MHz fRF = 898 MHz NF (Note 3) 3 fRF = 1598 MHz fRF = 2198 MHz fRF = 898 MHz Apsat (Note 3) 2 fRF = 1598 MHz fRF = 2198 MHz fd = 898 MHz, fud = 903 MHz IP3 (Note 3) 4 fd = 1598 MHz, fud = 1603 MHz fd = 2198 MHz, fud = 2203 MHz fRF = 898 MHz CGs (Note 3) 2 fRF = 1598 MHz fRF = 2198 MHz fosc = 1300 MHz DfB 2 fosc = 2000 MHz fosc = 2600 MHz fosc = 1300 MHz PN (with 10-kHz offset) 2 fosc = 2000 MHz fosc = 2600 MHz fosc = 1300 MHz LORF LO leak level 2 fosc = 2000 MHz fosc = 2600 MHz fosc = 1300 MHz LOIF LO leak level 2 fosc = 2000 MHz fosc = 2600 MHz Test Condition (Note 4) 3/4 3/4 3/4 Min 850 3/4 350 3/4 1300 27.5 27.5 25 3/4 3/4 3/4 6.5 6.5 6.5 15 15 15 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Typ. 3/4 3/4 3/4 75 3/4 31 31 29 9 9 11 8.5 8.5 8.5 18.5 17 17 3/4 3/4 3/4 3/4 3/4 3/4 -74 -75 -74 -40 -32 -32 -28 -32 -32.5 Max 2200 -35 550 3/4 2700 34 34.5 32.5 10.5 11 13 3/4 3/4 3/4 3/4 3/4 3/4 2 2 2 4.5 3.5 3.5 -70 -71 -70 -37 -29 -29 -20 -24 -27 dBmW dBmW dBc/ Hz MHz dB dBmW dBmW dB dB Unit MHz dBmW MHz W MHz
Noise figure
IF output power level
3rd inter modulation (IF output intercept point)
Conversion gain shift
Frequency shift (PLL OFF)
Phase noise
RF pin
IF pin
Note 3: IF output frequency = 402 MHz Note 4: IF output load = 75 W
8
2002-02-12
TA1296FN
PLL Block (unless otherwise specified, VCC1 = VCC2 = VCC3 = VCC4 = 5 V, Ta = 25C)
Parameter Tuning amplifier output voltage (close) Tuning amplifier maximum current X'tal negative resistance X'tal operating range X'tal external input level X'tal external input frequency Ratio setting range Logic input low voltage Logic input high voltage Logic input current (low) Logic input current (high) ACK output voltage Symbol Vt out Ivt XtR OSCin Xo extl X-ext N VIL VIH I BsL I BsH VACK Test Circuit 1 1 1 1 1 1 3/4 1 SDA and SCL pins 1 1 SDA and SCL pins 1 1 ISINK = 3 mA CP1 = [0], CP0 = [0] Charge pump output current Ichg 1 CP1 = [0], CP0 = [1] CP1 = [1], CP0 = [0] CP1 = [1], CP0 = [1] Band driver drive current Band driver voltage drop Comparator pin input voltage Comparator pin low voltage Comparator pin high voltage IBD VBDsat VCMP VLCMP VHCMP 1 1 1 1 1 B1, B2 B1, B2: IBD = 10-mA drive IP-1, IP-2, IP-3 IP-1, IP-2, IP-3 IP-1, IP-2, IP-3 1-kW, 10-pF load X'tal: NDK (AT-51), 4 MHz used. 4-MHz level monitored on oscilloscope using FET probe (1 MW, 1.9 pF). 3/4 2.4 -20 -10 3/4 35 75 180 375 3/4 3/4 0 0 2.7 XO-SW: VCC2 or open 16-bit counter Test Condition (Note 4) VBT = 33 V, RL = 33 kW VBT = 33 V XO-SW:GND (X'tal oscillator mode) [NDK (AT-51), 4 MHz used] Min 0.3 3/4 1 3.2 100 2 1024 -0.3 Typ. 3/4 3/4 2.5 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 50 100 240 490 3/4 3/4 3/4 3/4 3/4 Max 33 3 3/4 4.5 1000 6 65,535 1.5 VCC2 + 0.3 10 20 0.4 75 145 345 700 10 0.2 6 1.5 6 mA V V V V mA V V mA mA V Unit V mA kW MHz mVp-p MHz
Xo buffer output level
Xo out
1
350
500
mVp-p
9
2002-02-12
TA1296FN
Bus Line Characteristics
Parameter SCL clock frequency Bus free time between a STOP and START conditions Hold time for repeated START condition SCL clock low period SCL clock high period Set-up time for repeated START condition Data hold time Data set-up time Rise time for SDA and SCL signals Fall time for SDA and SCL signals Set-up time for STOP condition Symbol fSCL tBUF tHD; STA tLOW tHIGH fSU; STA tHD; DAT tSU; DAT tR tF tsU; STO 3/4 Please refer to data timing chart. Test Circuit Test Condition Min 0 4.7 4 4.7 4 4.7 0 250 3/4 3/4 4 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Max 100 3/4 3/4 3/4 3/4 3/4 3/4 3/4 1000 300 3/4 Unit kHz ms ms ms ms ms ms ns ns ns ms
SDA tBUF
tLOW SCL
tR
tF
tHD; STA
tHD; STA P S
tHD; DAT
tHIGH
tSU; DAT tSU; STA Sr
tSU; STO P
Figure 1
I C Bus Data Timing Chart (rising-edge timing)
2
10
2002-02-12
TA1296FN
Test Conditions
(1) Conversion gain RF input level = -40dBmW Noise figure NF meter direct-reading value (DSB measurement) IF output power level Measure maximum IF output level. 3rd inter modulation * fd (fd input level = -40dBmW) * fud = fd + 5 MHz (fud input level = -40dBmW) Calculate IF output intercept point as follows: IP3 = S/(N - 1) + P [dBmW] S: suppression level N: 3 P: IF output level Conversion gain shift Conversion gain shift is defined as change in conversion gain when supply voltage exceeds ranges VCC = 5 V to 4.5 V or VCC = 5 V to 5.5 V. Frequency shift (PLL OFF) Frequency shift is defined as change in oscillator frequency when supply voltage exceeds ranges VCC1 = 5 V to 4.5 V or VCC1 = 5 V to 5.5 V. Phase noise (offset = 10 kHz) Measure phase noise at 10-kHz offset. RF pin local-leak level Measure worst-case local-leak level for RF pin (with IF output pin open). IF pin local-leak level Measure worst-case local-leak level for IF pin (with RF input pins shorted using 50-W resistor).
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
11
2002-02-12
TA1296FN
PLL Block --I C Bus Communications Control-The TA1296FN conforms to Standard Mode I2C bus format. I2C Bus Mode allows two-way bus communication using Write Mode (for receiving data) and Read Mode (for processing status data). Write Mode or Read Mode can be selected by setting the least significant bit (R/W bit) of the address byte. If the least significant address bit is set to 0, Write Mode is selected; if it is set to 1, Read Mode is selected. Address can be set using the hardware bits. 4 programmable address can be programmed. Using this setting, multiple frequency synthesizers can be used on the same I2C bus line. The address for the hardware bit setting can be selected by applying voltage to the address setting pin (ADR-pin 25). The address is selected according to the setting of these bits. During acknowledgment of receipt of a valid address byte, the serial data (SDA) line is Low. If Write Mode is currently selected, when the data byte is programmed, the serial data (SDA) line will be Low during the next acknowledgment. A) Write mode (setting command) When Write Mode is selected, byte 1 holds address data; byte 2 and byte 3 hold frequency data; byte 4 holds frequency data, the divider ratio setting and function setting data; and byte 5 holds output port data. Data is latched and transferred at the end of byte 3, byte 4 and byte 5. Byte 2 and byte 3 are latched and transferred as a byte pair. Once a valid address has been received and acknowledged, the data type can be determined by reading the first bit of the next byte. That is, if the first bit is 0, the data is frequency data; if it is 1, the data is function-setting or band output data. Additional data can be input without the need to transmit the address data again until the I2C bus STOP condition is detected (e.g. a frequency sweep using additional frequency data is possible). If a data transmission is aborted, data programmed before the abort remains valid. [[BYTE 1]] The address data for byte 1 can be set using the hardware bit. The hardware bit can be set by applying a voltage to the address-setting pin (ADR: pin 25). [[BYTE 2, BYTE 3, (N15) in BYTE 4]] Byte 2 , byte 3 and N15 of byte 4 control the 16-bit programmable counter ratio and are stored in the 16-bit shift register together with frequency setting counter data. The program frequency can be calculated using the following formula: fosc = 2 fr N fosc: Program frequency fr: Phase comparator reference frequency N: Counter total divider ratio
2
fr is calculated from the crystal oscillator frequency and the reference frequency divider ratio set in byte 4 (the control byte). (fr = X'tal oscillator frequency/reference divider ratio) The reference frequency divider ratio can be set to 1/64 or 1/128. When a 4-MHz crystal oscillator is used, fr = 62.5 kHz or 31.25 kHz. The respective step frequencies are 125 kHz and 62.5 kHz. [[BYTE 4]] Byte 4 is a control byte used for selecting functions. Bit 4 (CP1) and bit 5 (CP0) determine the output current of the charge pump circuit. If bit 4 and bit 5 are set to [CP1]:[CP0] = 00, the output current is set to 50 mA. If bit 4 and bit 5 are set to [CP1]:[CP0] = 01, the output current is set to 100 mA. If bit 4 and bit 5 are set to [CP1]:[CP0] = 10, the output current is set to 240 mA. If bit 4 and bit 5 are set to [CP1]:[CP0] = 11, the output current is set to 490 mA. Bit 7 (Rs) can be used to set the X'tal reference frequency divider ratio. If bit 7 is set to 0, the X'tal divider ratio is 1/128 (with a frequency step of 62.5 kHz). If it is set to 1, the X'tal divider ratio is 1/64 (with a frequency step of 125 kHz). Bit 8 (OS) can be used to set the charge pump driver amplifier output setting. If bit 8 is set to 0, the output is ON (the normal setting). If it is set to 1, the output is OFF.
12
2002-02-12
TA1296FN
[[BYTE 5]] Byte 5 can be used to select Test Mode and to control the output ports (band 1 and band 2). Bit 1, bit 2 and bit 3 (T2, T1 and T0) can be used to set up Test Mode. These bits determine the phase comparator reference signal output and the counter divider output. Bit 5 (for B2) and bit 8 (for B1) can be used to control the output ports. When either of these bits is set to 0, the corresponding port is turned OFF. When either of these bits is set to 1, the corresponding port is turned ON. Each output port can be driven at less than 10 mA. B) Read mode (status request) When Read Mode is selected, the power-on reset operation status, phase comparator lock detector output status, comparator input port status and 5-level AD converter pin input voltage status are output to the master device. Bit 1 (POR) indicates the power-on reset operation status. When the power supply voltage VCC2 is cut off, this bit is set to 1. Bit 1 is reset to 0 when a voltage of 3 V or higher is applied to VCC2 and transmission is requested in Read Mode. At this point the new status is output. (bit 1 is also set to 1 when VCC2 is turned ON.) Bit 2 (FL) indicates the phase comparator lock status. When the phase comparator is locked, 1 is output. When the phase comparator is unlocked, 0 is output. Bit 3, bit 4 and bit 5 (I-P3, I-P2, I-P1) indicate the input comparator status. I-P3, I-P2 and I-P1 indicate the status of input ports I-P3, I-P2 and I-P1 (pins 13, 14 and 15) respectively. The input voltage status for each comparator input port pin is output to the master device. High is indicated by 1. Low is indicated by 0. High represents a voltage of above 2.7 V applied to the corresponding pin. Low represents an applied voltage of below 1.5 V. Bit 6, bit 7 and bit 8 (A2, A1 and A0) indicate the status of the five-level AD converter. The voltage applied to the AD converter input pin (pin 3) is output after being resolved to one of five levels. To see the bit values output for the five resolution levels and to see how these levels correspond to the voltage applied to the AD converter input pin (ADCin-pin 12), please refer to the table entitled A2, A1 and A0: Five-level AD converter status (e.g. the AFT output voltage data can be given to the master device).
Data Format
A) Write mode
MSB 1 2 3 4 5 Address Byte Divider Byte 1 Divider Byte 2 Control Byte Band SW Byte 1 0 N7 1 T2 1 N14 N6 T1 0 N13 N5 N15 T0 0 N12 N4 CP1 0 N11 N3 CP0 B2 MA1 N10 N2 MA0 N9 N1 Rs LSB R/W = 0 N8 N0 OS B1 ACK ACK ACK (L) ACK (L) ACK (L)
: Don't care ACK: Acknowledged (L): Latch and transfer timing B) Read mode
MSB 1 2 Address Byte Status Byte 1 POR 1 FL 0 I-P3 0 I-P2 0 I-P1 MA1 A2 MA0 A1 LSB R/W = 1 A0 ACK 3/4
ACK: Acknowledged
13
2002-02-12
TA1296FN
Data Specifications
* MA1 and MA0: programmable hardware address bits
MA1 0 0 1 1 MA0 0 1 0 1 Voltage Applied to Address Pin 0 to 0.1VCC2 OPEN or 0.2VCC2 to 0.3VCC2 0.4VCC2 to 0.6VCC2 0.9VCC2 to VCC2
* *
N15-N0: programmable counter data CP1 and CP0: charge pump output current setting
CP1 0 0 1 1 CP0 0 1 0 1 Output Current (mA) 50 (typ.) 100 (typ.) 240 (typ.) 490 (typ.)
*
Rs: reference frequency divider ratio selection bit.
Rsa 0 1 Divider Ratio 1/128 1/64 Step Frequency 62.5 kHz 125 kHz Phase Comparator Reference Frequency 31.25 kHz 62.5 kHz
*
OS: tuning amplifier control bit 0: Tuning amplifier ON (normal operation) 1: Tuning amplifier OFF
*
T2, T1 and T0: test mode setting bits
Parameter Normal operation OFF Charge pump SINK SOURCE Reference signal output 1/2 counter divider output Phase comparator test T2 0 0 1 1 1 1 0 T1 0 1 1 1 0 0 0 T0 0 1 0 1 1 Reference signal input: SCL Charge pump is OFF. Only charge pump sink current is ON. Only charge pump source current is ON. Reference signal output (check output: ADC) 1/2 counter output (check output: ADC) Comparative signal input: SDA Notes 3/4
: DON'T CARE Note 5: When Test Mode is used, the tuning amplifier control bit OS is 0, signifying normal operation. To test the counter divider output, programmable counter data input is required.
14
2002-02-12
TA1296FN
* B1 and B2: band output 0: OFF 1: ON * POR: power-on reset flag 0: Normal operation 1: Reset * FL: lock detect flag 0: Unlocked 1: Locked * I-P1, I-P2 and I-P3: comparator input status 0: Input voltage is below 1.5 V. 1: Input voltage is above 2.7 V. * A2, A1 and A0: five-level AD converter status
Voltage Applied to ADC Pin 0.60VCC2 to VCC2 0.45VCC2 to 0.60VCC2 0.30VCC2 to 0.45VCC2 0.15VCC2 to 0.30VCC2 0 V to 0.15VCC2 A2 1 0 0 0 0 A1 0 1 1 0 0 A0 0 1 0 1 0
Accuracy is (0.03 VCC2) * XO-SW: reference signal changeover switch
Pin 24 Status GND VCC2 or open Input Method X'tal input External input
15
2002-02-12
TA1296FN
Test Circuit 1
DC Characteristics
VCC4 (5 V) A ICC4 0.01 mF 1 nF 1 nF
ADR set
VCC2/Open
VCC3 (5 V) A ICC3 0.01 mF NC 21 20
R IBD1 A
SDA V Vsat
SCL
VCC2/Open: Extenal input GND: X'tal
XO-SW
30
29
28
27
26
25
24
23
22
19
18
17
16
ADR XO-SW Band Driver
Programmable Counter 1/2 1/32 1/33
Data Interface
Phase Comparator
Divider
ADC Charge Pump 0.01 mF 1 2 0.01 mF 3 NC 4 NC 5 6 NC 7 8 9 10 1 nF 11 12 13
Comparator
14
15
1 kW
*X'tal 22 pF
1 nF
A ICC1 VCC1 (5 V) NF
A ICC2 10 pF 4 MHz out ADC in I-P1 I-P2 I-P3
EXT.in VCC2 (5 V)
X'tal: NDK (AT-51), 4 MHz
16
2002-02-12
TA1296FN
Test Circuit 2
AC Characteristics
5V RF in ADR set VCC2/Open
VCC2/Open: Extenal input GND: X'tal
IF out
B2
B1
SDA
SCL
390 W 20 19 18 17 Band Driver Data Interface ADC Comparator 11 12 13 14 ADC in I-P1 I-P2
0.1 mF
1 nF
1 nF
30
29
28
27
26
25
24
1 nF
23
22
0.1 mF
XO-SW
21
16
ADR XO-SW
Programmable Counter 1/2 1/32 1/33
Phase Comparator
Divider
Charge Pump 0.01 mF 1 0.1 mF 1T379 L 2 3 4 10 kW 4.7 kW 1T379 5 5 pF 6 7 8 *X'tal 22 pF 9 10 1 nF 15
47 pF
4.7 nF
4.7 nF
13 kW
0.1 mF
4 MHz out
I-P3
33 V
47 kW
1 nF
X'tal: NDK (AT-51), 4 MHz
10 kW
17
2002-02-12
390 W
1 nF
TA1296FN
Test Circuit 3
Measuring Noise Figure
Noise Figure Meter
out
in
28
DUT
21 75 W-50 W impedance transformer
Test Circuit 4
Measuring 3rd Inter Modulation
fd Signal Generator 1
28
DUT
21 75 W-50 W impedance transformer
in
Spectrum Analyzer
Signal Generator 2 fud
18
2002-02-12
TA1296FN
I C-Bus Control Summary
The bus control format of TA1296FN conforms to the Philips I2C-bus control format.
2
Data Transmission Format
S Slave address 7 bits MSB MSB 0A SUB address 8 bits MSB A Data 8 bits AP
S: Start condition P: Stop condition A: Acknowledge (1) Start/stop condition
Serial Data
Serial Clock S Start condition P Stop condition
(2)
Bit transfer
Serial Data
Serial Clock
Serial data unchanged.
Serial data can be changed.
(3)
Acknowledge
Serial Data From Master Device
High-Impedance
Serial Clock From Slave
High-Impedance
Serial Clock From Master Device S
1
8
9
19
2002-02-12
TA1296FN
(4) Slave address
A6 1 A5 1 A4 0 A3 0 A2 0 A1 * A0 * R/W 0
Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Tights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
Handling Precautions
1. The device should not be inserted into or removed from the test jig while a voltage is being applied to it: otherwise the device may be degraded or break down. Also, do not abruptly increase or decrease the power supply to the device (see figure 1). Overshoot or chattering in the power supply may cause the IC to be degraded. To avoid this, filters should be placed on the power supply line.
6 V (VCC1, VCC2, VCC3, VCC4) 38 V (VBT) Supply voltage
90%
10%
1 ms
Time
Figure 1
2. The peripheral circuits described in this datasheet are given only as system examples for evaluating the device's performance. TOSHIBA intend neither to recommend the configuration or related values of the peripheral circuits nor to manufacture such application systems in large quantities. Please note that the high-frequency characteristics of the device may vary depending on the external components, the mounting method and other factors relating to the application design. Therefore, the evaluation of the characteristics of application circuits is the responsibility of the designer. TOSHIBA only guarantee the quality and characteristics of the device as described in this datasheet and do not assume any responsibility for the customer's application design. In order to better understand the quality and reliability of TOSHIBA semiconductor products and to incorporate them into designs in an appropriate manner, please refer to the latest Semiconductor Reliability Handbook (integrated circuits) published by TOSHIBA Semiconductor Company. This handbook can also be viewed on-line at the following URL: .
3.
20
2002-02-12
TA1296FN
Package Dimensions
Weight: 0.17 g (typ.)
21
2002-02-12
TA1296FN
RESTRICTIONS ON PRODUCT USE
000707EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
22
2002-02-12

▲Up To Search▲

Price & Availability of TA1296FN

	To Download TA1296FN Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .